In a large digital integrated circuit (IC) design, such as a large system-on-chip (SOC), there can be multiple embedded cores or hard intellectual properties (IPs). Due to the large design size and complexity of the functional IP types, the design is mostly partitioned into multiple physical partitions. For test and debugging purposes, the design is further divided into multiple designs for testing (DFT) partitions, which are often based on the functional and physical design partitions. Each of the embedded cores and hard IPs are often treated as separate partitions with some small IPs grouped into a bigger physical partition.
The physical partition approach, and similarly hierarchical design approach, is intended to better optimize the design for area and performance including timing/speed and low power. In a typical low-power high-performance SOC, there are also multiple power domains of which some of the embedded cores or hard IPs have separate power domains. The power for each embedded core may be separately switched on/off as required to achieve a low power goal and higher performance without encountering power or thermal issues in the chip. With multi-power domains in the design, there are often power management and power isolation circuits among the different power domains in the SOC.
In such physical partitions, mostly the embedded cores, often the DFT test wrapper cells are inserted around the input/outputs (I/Os) of the partition to isolate the cores during a test mode. The test wrapper cells provide controllability to the inputs, and added observability to the outputs in an internal core test (INTEST) mode, and vice versa in an external test (EXTEST) mode. So, on a common core, there may be power isolation cells in addition to test wrapper cells on the I/O paths since the core could have its own power domain and its own DFT partition. This leads to large delays to the I/O paths, an increase in circuit area, and an increase in power consumption.
Therefore, optimizing a core I/O structure is crucial to improving chip performance in both test and functional modes such as I/O paths, in particular critical I/O paths, optimizing for timing/speed, reducing logic and area overhead, as well as lowering power consumption.
The importance of a scan design in the overall physical implementation flow can be evidenced in all areas of the design. There have been numerous efforts in improving scan design from the scan insertion to the scan chain reordering and optimization in physical placement. In a typical low-power design with multiple power domains, power related cells, such as a power isolation cell, a level shifter, and a power gating cell, may be inserted on the I/Os of a core and IPs at the block boundary for low-power operations.
A typical method for test wrapper cell insertion for test purposes and power cell insertion for power isolation and low-power operations at the block boundary on I/O paths needs to provide a test operation and a low-power operation separately. Since the test wrapper cells and power cells are inserted to the same I/O paths in the design, this creates additional physical design and performance problems that have to be addressed during physical design process. Such problems include a highly congested I/O boundary with both the test wrapper and power cells and their associated logics. The I/O paths, in particular, some critical I/O paths, may experience speed and timing problems. Increased logic and area overhead for such logic and cells also present challenges. Other problems arise as well such as an increase in power consumption for such cells that contribute to an increase in overall chip power consumption.